This invention relates generally to integrated circuits and, more particularly, to integrated circuit MOSFET devices and methods for their manufacture.
Metal oxide semiconductor field effect transistors (MOSFETS) are basic electronic devices used in many integrated circuits (ICs). MOSFETS are typically formed in a semiconductor substrate by providing a gate structure over the substrate to define a channel region, and by forming source and drain regions on opposing sides of the channel region. A common variant of the basic MOSFET device is known as complementary metal oxide semiconductor (CMOS) device wherein two MOSFETS of opposing polarity types are coupled together to provide a single, functional CMOS transistor device.
An advantage of CMOS devices is that they have very low standby power requirements. Therefore, CMOS devices are well adapted for applications which require low-energy consumption. Furthermore, since CMOS devices consume less power than MOSFET devices or bipolar circuitry, CMOS devices tend to generate less heat than these other technologies, making them well suited for high-density circuitry which might otherwise require elaborate cooling mechanisms.
Integrated circuit designers continue to design integrated circuit devices with smaller and smaller feature sizes. For example, not too long ago it was not uncommon to have MOSFET devices (including CMOS devices) having channel lengths of 2 microns or more. The current state of the art for production MOSFET devices has 0.8 micron channel lengths. The next generation of high-density digital integrated circuitry, however, will be made with MOSFETS having channel lengths of 0.6 microns, and even shorter.
As the channel lengths of MOSFET devices have shrunk, MOSFETS have become more susceptible to certain problems. One of these problems is known as the "hot carrier" or "hot electron" effect wherein energetic carriers, typically electrons, are accelerated by high electric (E) fields within the channel and injected into the thin dielectric layer of the gate structure and into the thicker dielectric gate spacer structure. Over time, these hot electrons create a permanent charge in the thin dielectric layer and the dielectric spacers of the gate structure, degrading or destroying the performance of the associated MOSFET device. This is typically more of a problem with N-channel MOSFETS (which have electrons as the primary carrier species) than in P-channel MOSFETS (which have "holes" as the primary carrier species).
FIG. 1a illustrates a prior art lightly doped drain (LDD) MOSFET structure which is used to reduce the hot electron effect in MOSFET devices. As in all MOSFET devices, the LDD structure includes a source, a drain, and a gate structure. Theoretically, only the drain requires a lightly doped region to reduce the hot electron effect. However, the LDD structure typically includes two lightly doped regions, one of which is provided proximate to the drain and the other of which is provided proximate to the source for ease of manufacturability. A channel C of the LDD structure extends between the source LDD region and the drain LDD region. By providing the LDD regions, the electric field E proximate to the channel C is reduced, thereby producing fewer "hot electrons" which could be injected into the thin gate dielectric layer 0 or the spacers S of the gate structure.
The prior art LDD structure of FIG. 1a can be made by a variety of processes, but is typically made by providing a low-density ion implant of the LDD regions before adding oxide spacers S to the gate structure. After the spacers S have been added to the gate structure, a higher-density ion implant is made to form the source and drain regions. A subsequent annealing process is then typically performed to activate the implanted ions. Since the source and drain regions were implanted after the formation of the spacers S, they are offset farther from the center of the channel C than are the LDD regions.
As channel lengths have become shorter, it has become desirable to extend the lightly-doped regions farther into the channel region. A process known as the "large tilt-angle implant drain" (LATID) has been developed to provide a longer lightly doped region (thereby further reducing peak electric field strength) and to shift the peak electric field strength further underneath the gate oxide, thereby reducing injection of electrons into the thicker spacer dielectric. Both of these factors reduce the hot electron effect. The extended lightly-doped regions reduce the hot electron effect, vis-a-vis the LDD MOSFET structure.
With reference to FIG. 1b, a prior art LATID process forms the illustrated LATID structure. To create the LATID structure of FIG. 1b, a gate assembly is first formed over a semiconductor substrate W. Next, ions are implanted into the substrate W at an angle to form LATID regions on opposing sides of a channel region C. The angle of the ion implantation for the LATID regions is typically about 20-60 degrees. This forms lightly-doped LATID regions which extend farther beneath the gate assembly of the LATID structure. Next, the spacers S are formed against the gate structure, and source and drain implants take place to create the source and drain regions. Examples of LATID MOSFET structures are described in an article entitled "A New MOSFET with Large-Tilt-Angle Implanted Drain (LATID) Structure," IEEE Electron Device Letters, Vol. 9, No. 6, June 1988, by Takashi Hori and Kazumi Kurimoto, and in an article entitled "1/4.mu. LATID Technology for 3.3V Operation", Takashi Hori, 1989 IEDM.
Another problem which is encountered with MOSFET devices, is damage due to electrostatic discharge (ESD). This is particularly true of MOSFET devices used for integrated circuit input/output (I/O). With such I/O MOSFET devices, an electrostatic discharge on a lead of an integrated circuit can cause a high energy discharge across the I/O device, thereby destroying the device. Both LDD and LATID MOSFET structures are quite vulnerable to ESD.
FIG. 1c illustrates a prior art double diffused drain (DDD) MOSFET device which has a reduced vulnerability to ESD. The DDD MOSFET device of FIG. 1c involves the formation of medium to heavily doped DDD regions in the substrate W. Unfortunately, while the DDD MOSFET structure of FIG. 1c greatly reduces vulnerability to ESD, it has the undesired side-effect of increasing the hot electron effect and another problem known as the "short channel effect" compared to LDD or LATID MOSFET structures. The short channel effect occurs when the channel is so short that the gate can no longer fully shut off the flow of carriers through the channel region. With the short channel effect, the MOSFET devices tend to have high leakage currents, which increases power consumption and may degrade the functionality of the MOSFET device.
Several papers discussing the DDD structure include "MOSFET Drain Engineering for ESD Performance" by Yi-Hen Wei, 1992 EOS/ESD Symposium, Sep. 16, 1992; "ESD Phenomena in a Graded Junction Devices", Duvvury et al, Texas Instruments, Inc., IEEE/IRPS 1989; and "Process and Design Optimization for Advanced CMOS I/O ESD Protection Devices," Daniel et al, 1990 EOS/ESD Symposium Proceedings.